`timescale 1ns / 1ps

/*charset UTF-8*/
/* Counter可调进制计数器 */

module Counter(
           input clk,
           input rst,
           input [4:0] psc,
           output reg Q,
           output reg [4:0] cnt);// NORM: 缩进使用分行缩进，输入先写input 再写output，output一般而言属于reg寄存器类型

initial begin
    cnt <= 4'b0000;
    Q <= 1'b0;
end

always @(posedge clk or negedge rst) begin
    if (~rst) begin
        Q <= 1'b0;
        cnt <= 4'b0000;
    end else begin
        cnt = cnt + 4'b0001;
        // FIXME cnt的计数进位比psc规定的少1
        if (cnt == psc) begin
            Q <= 1'b1;
            cnt <= 4'b0000;
        end else begin
            Q <= 1'b0;
        end
    end
end

endmodule
